Signals generated in electronic circuits must often be synchronized with a clock signal. For example, in the flag generation circuitry of a first-in first-out (FIFO) memory device, a counter may be used to count the number of write clock pulses and read clock pulses. These counters must, in some cases, have one set of outputs which are synchronized with the leading edge of the clock pulse and have a second set of outputs which is synchronized with the trailing edge of a clock pulse.
A method used in the past to generate these two sets of outputs was to use two separate counters. However, it can be appreciated that it is desirable to have a single counter circuit which is able to generate both sets of outputs.